a. The Field of the Invention
This invention relates to the field of integrated circuit manufacturing. In particular, the invention relates to phase shifting techniques in the optical lithography patterning process.
b. Background Information
Lithography processing is a required and essential technology when manufacturing conventional integrated circuits. Many lithography techniques exist, and all lithography techniques are used for the purpose of defining geometries, features, lines, or shapes onto an integrated circuit die or wafer. In general, a radiation sensitive material, such as photoresist, is coated over a top surface of a die or wafer to selectively allow for the formation of the desired geometries, features, lines, or shapes.
One known method of lithography is optical lithography. The optical lithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor wafer. A mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the aforementioned photoresist coated wafer. Light is then shone on the mask via a visible light source or an ultra-violet light source. In almost all cases, the light is reduced and focused via an optical lens system which contains one or several lenses, filters, and or mirrors. This light passes through the clear regions of the mask and exposes the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
In recent years, there has been great demand to increase the number of transistors on a given size wafer. Meeting this demand has meant that integrated circuit designers have had to design circuits with smaller minimum dimensions. However, prior to the work of Levenson, et. al., as reported in xe2x80x9cImproving Resolution in Photolithography with a Phase Shifting Mask,xe2x80x9d IEEE Transactions on Electron Devices, VOL., ED-29, November 12, December 1982, pp. 1828-1836, it was found that the traditional optical lithography process placed real limits on the minimum realizable dimension due to diffraction effects. For, at integrated circuit design feature sizes of 0.5 microns or less, the best resolution has demanded a maximum obtainable numerical aperture (NA) of the lens systems. However, as the depth of field of the lens system is inversely proportional to the NA, and since the surface of the integrated circuit could not be optically flat, good focus could not be obtained when good resolution was obtained and vice versa. Thus, as the minimum realizable dimension is reduced in manufacturing processes for semiconductors, the limits of optical lithography technology are being reached. In particular, as the minimum dimension approaches 0.1 microns, traditional optical lithography techniques will not work effectively.
One technique, described by Levenson, et. al., to realize smaller minimum device dimensions, is called phase shifting. In phase shifting, the destructive interference caused by two adjacent clear areas in an optical lithography mask is used to create an unexposed area on the photoresist layer. This is accomplished by making use of the fact that light passing through a mask""s clear regions exhibits a wave characteristic such that the phase of the amplitude of the light exiting from the mask material is a function of the distance the light travels in the mask material. This distance is equal to the thickness of the mask material. By placing two clear areas adjacent to each other on a mask, one of thickness t1 and the other of thickness t2, one can obtain a desired unexposed area on the photoresist layer through interference. For, by making the thickness t2 such that (nxe2x88x921)(t2) is exactly equal to {fraction (1/2 )} xcex, where xcex is the wavelength of the light shone through the mask material, and n is the refractive index of the material of thickness t1, the amplitude of the light exiting the material of thickness t2 will be 180 degrees out of phase with the light exiting the material of thickness t1. Since the photoresist material is responsive to the intensity of the light, and the opposite phases of light cancel where they overlap, a dark unexposed area will be formed on the photoresist layer at the point where the two clear regions of differing thicknesses are adjacent.
Phase shifting masks are well known and have been employed in various configurations as set out by B. J. Lin in the article, xe2x80x9cPhase-Shifting Masks Gain an Edge,xe2x80x9d Circuits and Devices, March 1993, pp. 28-35. The configuration described above has been called alternating phase shift masking (APSM). In comparing the various phase shifting configurations, researchers have shown that the APSM method can achieve dimension resolution of 0.25 microns and below.
One problem with the APSM method is that dark lines on the photoresist layer are created at all areas corresponding to 0 degree to 180 degree transitions in the mask. These dark lines, unless part of the desired end structure, should be erased at some point in the processing of the wafer.
Another problem is that the APSM method does not lend itself well to process technology shrinking. Traditionally, designers design an integrated circuit for a predetermined minimum realizable dimension. However, because process technologies can require a considerable amount of time to fine tune, the integrated circuit is first manufactured using a process technology that does not support the designed for speed and has a larger minimum dimension. Often, a first set of masks are created to manufacture the integrated circuits at the larger dimension. As the process technology improves, the minimum realizable dimension decreases. Additional mask sets are created for each new minimum dimension process. These masks are generally created using software driven machines to automatically manufacture the masks given the design features needed. However, due to the complexity of the masks needed to erase the aforementioned unwanted dark lines created when the APSM method is used, these masks have not generally been able to be designed automatically by mask creation programs. This has required mask designers to expend large amounts of time and money manually creating mask layouts when the APSM method is used.
Spence, U.S. Pat. No. 5,573,890, reveals one method to overcome these problems. Spence discloses a system in which phase shifting is used to shrink integrated circuit design, specifically to shrink transistor gate lengths, where the masks used are computer designed. The computer designs a mask or masks which achieve(s) the required minimum dimension and which provide for the removal of the unwanted dark lines created by the APSM method. In a disclosed single mask method, Spence uses transition regions to compensate for the unwanted dark lines that would have been produced where there were 0 degree to 180 degree transitions in the mask. The problem with this single mask method is that the single mask that results is complicated and difficult to manufacture. Further, the mask that is produced is very unlike the design of the circuit from a visual standpoint, thus making it difficult for designers to visually double check their work.
Spence also discloses a two mask method which is illustrated in FIG. 1. Old mask 100 represents a typical mask that would be used to produce a structure having a transistor of old gate length 109, which is wide enough to be achieved using traditional optical lithography techniques with no phase shifting. New gate length 159 is the desired transistor gate length that is smaller than the smallest dimension realizable through the process of traditional optical lithography. Spence uses a phase shift and structure mask 110 and a trim mask 120 in order to achieve the new gate length 159 and to remove the unwanted dark lines created by the phase shift method, respectively.
The phase shift and structure mask 110 is designed such that it contains both a structure chrome area 113, which is the same shape as the desired polysilicon structure of the circuit, and a phase shifter consisting of a 180 degree phase clear area 112 adjacent to a 0 degree phase clear area 111. When light is shined on the phase shift and structure mask 110, the phase shift and structure image 130 is created on the underlying photoresist layer. The phase shift and structure image 130 contains the desired final structure dark area 133 and the desired dark area 132, but also includes unwanted artifacts 135 created by interference at the transitions between the 180 degree phase clear area 112 and the 0 degree phase clear area 111.
Thus, in order to remove these unwanted artifacts 135 and achieve the desired result image 150, Spence discloses using the trim mask 120 solely to perform this function. The trim mask 120 consists of a chrome area 123 and an erasure light area 122. When light is shown on the trim mask 120, the trim image 140 is created on the photoresist layer. This trim image 140 contains an erasure light area 142 which serves to erase the unwanted artifacts 135. The result image 150 represents the final image created on the photoresist layer as a result of the two mask method disclosed by Spence.
Spence""s two mask method has several problems. By combining the production of the final structure and the phase shifting onto a single mask, this method introduces a large number of possible conflicts in the design rules of the circuit as a whole. This increase in conflicts makes it much more difficult for the computer to determine a solution to the shrinking of the circuit design that is within the design rules parameters. In addition, this increase in conflicts may in some instances produce a situation where no shrunk design is possible. Furthermore, combining the structure and phase shifting on one of the two masks increases the overall complexity of this mask thus making it more difficult to manufacture and inspect. Finally, combining structure and phase shifting on a single mask results in the design of a mask that does not look like the structure masks used for the earlier larger versions of the designed circuit. As a result, it is more difficult for the designers of the integrated circuit to visually check their work.
Therefore, what is desired is an improved method of using phase shifting to achieve smaller minimum realizable dimensions.
A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs is described.
One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.
Although many details have been included in the description and the figures, the invention is defined by the scope of the claims. Only limitations found in those claims apply to the invention.